Impact of HKMG and FDSOI FeFET drain current variation in processing-in-memory architectures

In this study, we analyze the impact of drain current ( $$ I_{{{\text{DS}}}} $$ ) variation in 28 nm high-K metal-gate and 22 fully-depleted silicon-on-insulator Ferroelectric FET devices on processing-in-memory (PIM) deep neural network (DNN) accelerators. When performing repeated read operations several at various frequencies under biasing programming conditions, non-Normal is observed. Device-circuit co-analysis used to emulate PIM performance subject noise when classifying images. Marginal degradation observed Fashion-MNIST classification accuracy using LeNet-5, more significant CIFAR-10 MobileNetV2. Variation-aware training shown fully recover minor drops LeNet-5 but becomes difficult for large workloads like We demonstrate that individual FeFETs over many cycles not prohibitive designing DNN accelerators with small workloads, advanced design techniques are required mitigate error larger workloads.